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Computer Architecture: Von Neumann, CPU Cycle & Memory

Computer architecture essentials: Von Neumann components, fetch-decode-execute cycle, memory hierarchy, interrupts, DMA, and bus systems.

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Computer Architecture: Von Neumann, CPU Cycle & Memory

Computer Architecture – Overview

This post is a conceptual guide to computer architecture, covering key principles, essential terminology, and core concepts.

In a Nutshell

The Von Neumann architecture is the foundational model for modern computers: the CPU fetches instructions and data from shared memory over a shared bus (a potential bottleneck).

The Von Neumann Architecture (Foundational Model)

Main components:

  1. Arithmetic Logic Unit (ALU)
  2. Control Unit
  3. Memory for both program and data
  4. Input/Output (I/O)

All components connect via a shared bus. This creates the Von Neumann bottleneck because instructions and data compete for the same pathway.

The CPU – the “Brain”

Typical execution flow: Fetch → Decode → Execute → Writeback.

Key concepts:

  • Registers (fast, small, on the CPU)
  • Instruction set (e.g., x86/ARM); CISC vs. RISC
  • Clock frequency (GHz) is not the only performance metric
  • Multiple cores enable parallel processing

Memory Hierarchy

From fastest/most expensive to slowest/cheapest:

  1. Registers
  2. Cache (L1/L2/L3)
  3. RAM
  4. SSD/Hard disk

Cache relies on the principle of locality:

  • Spatial locality
  • Temporal locality

Peripherals and Bus Systems

  • Bus types: data bus, address bus, control bus

I/O methods:

  • Programmed I/O (polling)
  • Interrupt-driven I/O
  • DMA (Direct Memory Access): data transfers directly between a device and RAM without constant CPU intervention

Performance Evaluation

Performance depends on more than just GHz:

  • IPC (Instructions per Cycle)
  • Number of cores
  • Memory latency and bandwidth

Exam Answer (Oral)

A computer is a machine that operates according to the Von Neumann architecture.
A CPU (ALU plus control unit) fetches instructions and data from shared memory
over a bus, performs calculations, and writes results back. To compensate for
slow memory access, the system uses a memory hierarchy with fast caches. I/O is
managed via interrupts or DMA to reduce CPU overhead.
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