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Computer Architecture Von Neumann Principle Fetch Decode Execute Cache Interrupt DMA

Computer Architecture: Von Neumann, CPU Cycle & Memory Hierarchy

Master computer architecture: Von Neumann components, CPU fetch-decode-execute, memory hierarchy, interrupts, DMA & bus systems.

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schutzgeist

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Computer Architecture: Von Neumann, CPU Cycle & Memory Hierarchy

Computer Architecture – Overview

This article is a term definition for computer architecture – including exam formula, key concepts, and tags.

In a Nutshell

The Von Neumann principle is the foundational model of modern computers: the CPU fetches instructions and data from a shared memory via a shared bus (potential bottleneck).

The Von Neumann Principle (Foundational Model)

Main components:

  1. Arithmetic Logic Unit (ALU)
  2. Control Unit
  3. Memory for program and data
  4. Input/Output (I/O)

All components are coupled via a shared bus. This creates the Von Neumann bottleneck, because instructions and data use “the same path”.

CPU – the “Brain”

Typical sequence: Fetch → Decode → Execute → Writeback.

Important concepts:

  • Registers (fast, small, in the CPU)
  • Instruction set (e.g., x86/ARM); CISC vs. RISC
  • Clock frequency (GHz) is not the only performance metric
  • Multi-core enables parallel processing

Memory Hierarchy

From fast/expensive to slow/cheap:

  1. Registers
  2. Cache (L1/L2/L3)
  3. RAM
  4. SSD/Hard Drive

Cache exploits the principle of locality:

  • spatial locality
  • temporal locality

Peripherals & Bus Systems

  • Bus: data bus, address bus, control bus

I/O methods:

  • Programmed I/O (Polling)
  • Interrupt-driven I/O
  • DMA (Direct Memory Access): data transfers directly between device and RAM without constant CPU involvement

Performance Evaluation

Performance depends not only on GHz, but also on:

  • IPC (Instructions per Cycle)
  • Number of cores
  • Memory latency/bandwidth

Exam Formula (Oral)

A computer is a machine that operates according to the Von Neumann principle.
A CPU (ALU + control unit) fetches instructions and data from a shared memory
via a bus, performs calculations, and writes results back. To compensate for
slow memory access, there is a memory hierarchy with fast caches. I/O is
organized via interrupts or DMA to reduce CPU overhead.
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